The fibre channel (“FC”) is an architecture and protocol for a data communications network for interconnecting computers and peripheral devices. The FC supports a variety of upper-level protocols, including the small computer systems interface (“SCSI”) protocol. A computer or peripheral device is linked to the network through an FC port and an FC link comprising copper wires or optical fibres, the computer or peripheral device, FC port, and FC link together referred to as an “FC node.” An FC port includes a transceiver and an interface controller, and the computer or peripheral device in which the FC port is contained is called a “host.” Hosts generally contain one or more processors, referred to as the “host processor” in the current application. The FC port exchanges data with the host via a local data bus, such as a peripheral computer interface (“PCI”) bus. The interface controller conducts lower-level protocol exchanges between the fibre channel and the computer or peripheral device in which the FC port resides.
An interface controller within an FC port serves essentially as a transducer between the serial receiver and transmitter components of the FC port and the host processor of the FC node in which the FC port is contained. The interface controller is concerned with, on the input side, assembling serially-encoded data received from the receiver component into ordered sets of bytes, assembling a majority of the ordered sets of bytes into basic units of data exchange, called “FC frames,” and passing the FC frames, along with status information, to the host processor within the context of larger collections of FC frames, called FC sequences and FC exchanges. On the output side, the interface controller accepts host memory buffer references and control information from the host processor, transforms them into FC frames, within higher-level contexts of FC sequences and FC exchanges, and provides the FC frames to the transmitter component of the FC port for serial transmission to the FC. The interface controller also exchanges lower-level control messages with remote nodes via the FC that are used for configuring the FC, maintaining state within FC nodes, establishing temporary paths between nodes, arbitrating control of FC loops, acknowledging receipt of FC data frames, and extending data transfer credits to remote nodes, among other things.
The interface controller communicates with the host processor through a set of host memory-based data structures and through a number of control registers accessible to both the interface controller and the host processor via a local bus, such as a PCI bus. At any given instant, the interface controller may be handling outgoing FC frames associated with different FC sequences, and may be also handling inbound FC frames from the FC associated with a number of FC sequences. The interface controller uses internal caches to cache information from the host memory-based data structures with which the interface controller communicates with the host processor.
The interface controller plays an analogous function within an FC port as that played by a computer processor in a multi-tasking operating system environment. The interface controller handles many different events concurrently with extremely dynamic patterns of state changes and information flow. The state of an interface controller is maintained in a number of different dynamic data structures and queues, generally stored within host memory, and accessible to both the interface controller and the host. The state of each currently active FC exchange and FC sequence is maintained in these data structures, as well as descriptors that reference incoming and outgoing frames, completion messages for write and read operations, and other such information.
I/O operations may be conducted within the context of a SCSI I/O operation embedded within the FC protocol. An I/O operation is initiated by an initiator node in order to read data from, or write data to, a target node. At the conclusion of a write or read operation (“I/O operation”), the initiator node generally receives a FC response frame from the target node, whether or not the I/O operation successfully completes. This FC response frame is received by the interface controller from the FC, the data contents of the FC response frame are transferred to a buffer in host memory, and a completion notice is placed into a separate completion queue in host memory by the interface controller. Thus, data is sent from the interface controller to two different host memory locations upon reception by the initiating node of a response FC frame.
In FC controllers, as in operating systems and other real-time device controllers, queues are employed for buffering output data and input data. In a typical FC controller, inbound frames are received by the FC interface controller from the transceiver component of the FC node that contains the FC interface controller and placed into an inbound first-in-first-out (“FIFO”) queue within the FC interface controller. Outbound frames are created by the FC controller in response to queuing, by the host computer, of an I/O request into a host memory queue. The FC controller creates FC frames and queues them to an outbound FIFO queue.
FC frames include FC data frames and FC link-control frames. One type of FC link-control frame is an acknowledgement (“ACK”) frame. An FC node sends ACK frames to remote nodes from which the FC node has received FC data frames in order to acknowledge receipt of the FC data frames. FC nodes employ an end-to-end (“EE”) credit management strategy in which an FC node must obtain credits prior to transmitting FC frames to a remote node. In addition to acknowledging receipt of an FC frame, ACK frames are used to transfer credits to a remote node to allow the remote node to send additional frames to an FC node.
An outbound sequence manager (“OSM”) component of an interface controller is responsible for receiving outbound descriptor blocks (“ODBs”) that describe FC sequences to be transmitted to remote FC nodes, constructing the FC frames for the FC sequences using references to host memory data within the ODB describing the FC sequences, and queuing the FC frames to an outbound FIFO queue. In addition, the OSM receives ACK frames form an inbound FIFO that allow additional FC frames to be sent to remote FC nodes. The OSM interacts with host memory, a component that provides ODBs, a component that manages inbound FC frames, and the outbound FIFO, internally maintaining context information about a number of active FC sequences, receiving and processing link control frames, and creating FC frames and queuing the FC frames to the outbound FIFO manager.
The OSM receives many different types of signals and data and outputs various types of signals and FC frames while internally managing a number of active contexts. Current OSM implementations involve multiple finite state machines (“FSMs”). However, because of the complexity of signal processing, data processing, and data generation, the performance of current OSMs is negatively impacted by the complexity of the FSMs required to track and integrate many asynchronous control signals and by the complex intercommunications needed between FSMs in order to maintain overall state information across multiple FSMs. Moreover, as the number and complexity of FSMs increases, it becomes increasingly difficult to design, test, and verify correct operation of multiple FSMs. Designers and manufacturers of complex control hardware, such as OSMs, have recognized a need for implementing control hardware more simply and more efficiently in order to decrease latency of operation, to increase throughput, or, in other words, the rate of decision making and data generation, and to decrease the complexity of design and verification.